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CY2SSTV857-32
Differential Clock Buffer/Driver DDR400/PC3200-Compliant
Features
* Operating frequency: 60 MHz to 230 MHz * Supports 400-MHz DDR SDRAM * 10 differential outputs from one differential input * Spread-Spectrum-compatible * Low jitter (cycle-to-cycle): < 75 * Very low skew: < 100 ps * Power management control input * High-impedance outputs when input clock < 20 MHz * 2.6V operation * Pin-compatible with CDC857-2 and -3 * 48-pin TSSOP and 40 QFN package * Industrial temperature of -40C to 85C * Conforms to JEDEC DDR specification
Description
The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV857-32 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs.
Block Diagram
3 2
Pin Configuration
Y0 Y0# Y1 Y1# Y2 Y2# Y3 Y3# Y4 Y4# Y5 Y5# Y6 Y6# Y7 Y7# Y8 Y8# Y9 Y9# FBOUT FBOUT#
VS S Y0 # Y0 VD D Q Y1 Y1 # VS S VS S Y2 # Y2 VD D Q VD D Q CLK C LK# VD D Q AVD D AVS S VS S Y3 # Y3 VD D Q Y4
32 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VS S Y5 # Y5 VD D Q Y6 Y6 # VS S VS S Y7 # Y7 VD D Q PD# FB IN FB IN # VD D Q FB O U T # FB O U T VS S Y8 # Y8 VD D Q Y9 Y9 # VS S
PD 37 AVDD 16
Test and Powerdown Logic
5 6 10 9 20 19 22 23 46 47 44 43
CY2SSTV857-32
CLK CLK# FBIN FBIN#
13 14 36 35
39 40
PLL
29 30 27 26
Y4 # VS S
48 TSSOP Package
Cypress Semiconductor Corporation Document #: 38-07557 Rev. *E
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 12, 2005
CY2SSTV857-32
40 QFN Package
VDDQ VDDQ Y1# Y0# Y5# Y1 Y0 Y5 Y6 Y6#
VSS Y2# Y2 VDDQ CLK CLK# VDDQ AVDD AVSS VSS
1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34 33 32 31
30 29 28
Y7# Y7 VDDQ PD# FBIN FBIN# VDDQ VDDQ FBOUT# FBOUT
40 QFN CY2SSTV857-32
27 26 25 24 23 22
10 11 12 13 14 15 16 17 18 19 20 21 Y3# Y4# Y9#
Y4
Y9
Y8
y3
VDDQ
Pin Description
Pin # 48 TSSOP 13, 14 35 36 3, 5, 10, 20, 22 2, 6, 9, 19, 23 5,6 25 26 37,39,3,12,14 36,40,2,11,15 Pin # 40 QFN Pin Name CLK, CLK# FBIN# FBIN Y(0:4) Y#(0:4) Y(9:5) Y#(9:5) FBOUT I/O[1] I I I O O O O O Pin Description Differential Clock Input. Electrical Characteristics LV Differential Input
Feedback Clock Input. Connect to FBOUT# for Differential Input accessing the PLL. Feedback Clock Input. Connect to FBOUT for accessing the PLL. Clock Outputs. Clock Outputs. Clock Outputs. Clock Outputs. Feedback Clock Output. Connect to FBIN for Differential Outputs normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Feedback Clock Output. Connect to FBIN# for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Power Down Input. When PD# is set HIGH, all Q and Q# outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q# outputs are disabled Hi-Z and the PLL is powered down. 2.6V Power Supply for Output Clock Buffers. 2.6V Nominal 2.6V Power Supply for PLL. When VDDA is at 2.6V Nominal GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (PD# = 0), the PLL is powered down. Common Ground. Analog Ground. 0.0V Ground 0.0V Analog Ground Differential Outputs Differential Outputs
27, 29, 39, 44, 46 17,19,29,32,34 26, 30, 40, 43, 47 16,20,30,31,35 32 21
33
22
FBOUT#
O
37
27
PD#
I
4, 11,12,15, 21, 28, 34, 38, 45 16
4,7,13,18,23,24, 28,33,38 8
VDDQ AVDD
1, 7, 8, 18, 24, 25, 1,10 31, 41, 42, 48 17 9
VSS AVSS
Note: 1. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07557 Rev. *E
VDDQ
Y8#
Page 2 of 9
CY2SSTV857-32
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV857-32 will likely be in a nested clock tree application. For these applications, the CY2SSTV857-32 offers a differential clock input pair as a PLL reference. The CY2SSTV857-32 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Table 1. Function Table Inputs AVDD GND GND X X 2.6V 2.6V 2.6V PD# H H L L H H H CLK L H L H L H < 20 MHz CLK# H L H L H L < 20 MHz Y L H Z Z L H Hi-Z Y# H L Z Z H L Hi-Z Outputs FBOUT L H Z Z L H Hi-Z FBOUT# H L Z Z H L HI-Z PLL BYPASSED/OFF BYPASSED/OFF Off OFF On On Off When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes.
Power Management
Output enable/disable control of the CY2SSTV857-32 allows the user to implement power management schemes into the design. Outputs are three-stated/disabled when PD# is asserted LOW (see Table 1).
CLKIN
FBIN t(phase error)
FBOUT
Yx tsk(o)
Yx
Yx tsk(o)
Figure 1. Phase Error and Skew Waveforms Document #: 38-07557 Rev. *E Page 3 of 9
CY2SSTV857-32
CLKIN
Yx or FBIN
tpd
Figure 2. Propagation Delay Time tPLH, tPHL
Yx
tC(n) tC(n+1)
Figure 3. Cycle-to-cycle Jitter
= 2.5" DDR _SDRAM represents a capacitive load CLK 120 Ohm CLK# PLL
= 0.6" (Split to Terminator)
DDR SDRAM VTR
FBIN 120 Ohm FBIN# FBOUT FBOUT# 0.3"
VCP DDR SDRAM
120 Ohm
Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF
Figure 4. Clock Structure # 1
Document #: 38-07557 Rev. *E
Page 4 of 9
CY2SSTV857-32
= 2.5" DDR-SDRAM represents a capacitive load CLK 120 Ohm CLK# VTR FBIN 120 Ohm FBIN# FBOUT
DDR-SDRAM
= 0.6" (Split to Terminator)
DDR-SDRAM
PLL
DDR-SDRAM
DDR-SDRAM Stack
VCP
DDR-SDRAM
120 Ohm
DDR-SDRAM Stack
FBOUT# 0.3"
Output load capacitancce for 4 DDR-SDRAM Loads: 10 pF < CL < 16 pF
Figure 5. Clock Structure # 1
VDDQ
VDDQ
V D D Q /2 14 pF
OUT
60 O hm
VTR RT = 120 O hm
OUT#
60 O hm
14 pF V D D Q /2
VCP
R e c e iv e r
Figure 6. Differential Signal Using Direct Termination Resistor
Document #: 38-07557 Rev. *E
Page 5 of 9
CY2SSTV857-32
Absolute Maximum Conditions[2]
Input Voltage Relative to VSS:...............................VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ........... VDDQ + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum Power Supply: ................................................3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDDQ. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDDQ). Min. 2.375 - 0.7 x VDDQ CLK, FBIN CLK, FBIN 0.36 Typ. - - - - Max. 2.625 0.3 x VDDQ - VDDQ + 0.6 (VDDQ/2) + 0.2 10 - - 0.6 - VDDQ - 0.4 (VDDQ/2) + 0.2 10 300 12 100 3.5 Unit V V V V V A mA mA V V V V A mA mA A pF
DC Electrical Specifications[3]
Parameter VDDQ VIL VIH VID VIX IIN IOL IOH VOL VOH VOUT VOC IOZ IDDQ IDD IDDS Cin Description Supply Voltage Input Low Voltage Input High Voltage Differential Input Voltage[4] Differential Input Crossing Voltage[5] Output Low Current Output High Current Output Low Voltage Output High Voltage Output Voltage Swing[6] Output Crossing Voltage[7] Operating PD#
Condition
(VDDQ/2) - 0.2 VDDQ/2 -10 26 28 - 1.7 1.1 - 35 -32 - - -
Input Current [CLK, FBIN, PD#] VIN = 0V or VIN = VDDQ VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT = 1V VDDQ= 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = -12 mA
High-Impedance Output Current VO = GND or VO = VDDQ Dynamic Supply Current[8] All VDDQ, FO = 200 MHz PLL Supply Current Standby Supply Current Input Pin Capacitance VDDA only PD# = 0 and CLK/CLK# = 0 MHz
(VDDQ/2) - 0.2 VDDQ/2 -10 - - - - 2 235 9 - -
AC Electrical Specifications [9, 10]
Parameter fCLK tDC tLOCK DTYC tsl(o) tPZL, tPZH Description Operating Clock Frequency Input Clock Duty Cycle Maximum PLL Lock Time Duty Cycle[11] Output Clocks Slew Rate Output Enable Time[12] (all outputs) Time[12] (all 60 MHz to 100 MHz 101 MHz to 170 MHz 20%-80% of VOD Condition AVDD, VDDQ = 2.6V 0.1V Min. 60 40 - 49 48 1 - 3 Typ. - - - 50 - Max. 230 60 100 51 52 2 25 Unit MHz % s % % V/ns ns
tPLZ, tPHZ Output Disable outputs) - 3 8 ns Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Unused inputs must be held HIGH or LOW to prevent them from floating. 4. Differential input signal voltage specifies the differential voltage VTR-VCPI required for switching, where VTR is the true input level and VCP is the complementary input level. See Figure 6. 5. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signal must be crossing. 6. For load conditions see Figure 6. 7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120 resistor. See Figure 6. 8. All outputs switching load with 14 pF in 60 environment. See Figure 6. 9. Parameters are guaranteed by design and characterization. Not 100% tested in production. 10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down spread or -0.5%. 11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWHC/tC, where the cycle time(tC) decreases as the frequency goes up. 12. Refers to transition of non-inverting output. Document #: 38-07557 Rev. *E Page 6 of 9
CY2SSTV857-32
AC Electrical Specifications(continued)[9, 10]
Parameter tCCJ tjit(h-per) tPLH(tPD) tPHL(tPD) tSK(O) tPHASE Half-period Description Cycle to Cycle Jitter [10] jitter[10, 13] Low-to-High Propagation Delay, CLK to Y High-to-Low Propagation Delay, CLK to Y Any Output to Any Output Skew[14] Phase Error
[14]
Condition f > 66 MHz f > 66 MHz Test Mode only
Min. -75 -100 1.5 1.5 - -50
Typ. - - 3.5 3.5 - -
Max. 75 100 7.5 7.5 100 50
Unit ps ps ns ns ps ps
Ordering Information
Part Number CY2SSTV857ZC-32 CY2SSTV857ZC-32T CY2SSTV857LFC-32[15] CY2SSTV857LFC-32T[15] CY2SSTV857ZI-32 CY2SSTV857ZI-32T CY2SSTV857LFI-32[15] CY2SSTV857LFI-32T[15] Lead-Free CY2SSTV857ZXC-32 CY2SSTV857ZXC-32T CY2SSTV857LFXC-32[15] CY2SSTV857LFXC-32T CY2SSTV857ZXI-32 CY2SSTV857ZXI-32T
[15]
Package Type 48-pin TSSOP 48-pin TSSOP-Tape and Reel 40-pin QFN 40-pin QFN-Tape and Reel 48-pin TSSOP 48-pin TSSOP-Tape and Reel 40-pin QFN 40-pin QFN-Tape and Reel 48-pin TSSOP 48-pin TSSOP-Tape and Reel 40-pin QFN 40-pin QFN-Tape and Reel 48-pin TSSOP 48-pin TSSOP-Tape and Reel
Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C
857-32 0327L11 *SWR#
Marketing Part Number Date Code and Fab Location Lot Code
Figure 7. Actual Marking on the Device
Notes: 13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 14. All differential input and output terminals are terminated with 120/16 pF, as shown in Figure 5. 15. The ordering part number differs from the marking on the actual device. See Figure 7 for the actual marking on the device.
Document #: 38-07557 Rev. *E
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CY2SSTV857-32
Package Drawing and Dimension
0.500[0.019]
24
48-lead (240-mil) TSSOP II Z4824
1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG.
25
48
12.395[0.488] 12.598[0.496]
1.100[0.043] MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030]
0.100[0.003] 0.200[0.008]
51-85059-*C
40-lead QFN 6 x 6 MM LF40A
TOP VIEW SIDE VIEW BOTTOM VIEW
0.08[0.003] A 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] N 1 0.60[0.024] DIA. 2 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF.
C
0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018]
5.70[0.224] 5.80[0.228]
5.90[0.232] 6.10[0.240]
0.30[0.012] 0.50[0.020]
(PAD SIZE VARY BY DEVICE TYPE)
0-12
0.50[0.020] C 4.45[0.175] 4.55[0.179]
0.24[0.009] 0.60[0.024]
(4X)
SEATING PLANE
51-85190-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07557 Rev. *E
Page 8 of 9
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
4.45[0.175] 4.55[0.179]
E-PAD
CY2SSTV857-32
Document History Page
Document Title: CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Document Number: 38-07557 REV. ** *A ECN No. 128403 129080 Issue Date 08/04/03 09/05/03 Orig. of Change RGL RGL New Data Sheet Changed the maximum operating frequency from 200 MHz to 250 MHz Added Industrial Temperature Range Changed the power supply from 2.5V to 2.6V Changed the supply voltage from 2.38, 2.5 and 2.63V to 2.3, 2.6 and 2.7V, respectively, in the DC Electrical Specifications table Changed the Fo value from 170 MHz to 200 MHz in the DC Electrical Specifications table Changed the Duty Cycle from 49.5 and 50.5 to 49 and 51% (60 to 170 MHz) Changed the Duty Cycle from 49 and 51 to 48 and 52% (101 to 170 MHz) Changed the half period jitter from 100 and 100 ps to 75 and 75 ps in the AC Electrical Specifications table Corrected QFN pinouts in the block diagram and in the Pin Description table Changed the Operating Frequency from 250 MHz to 230 MHz Changed Half Period Jitter and propagation delay Added Lead-free devices except the 40 QFN industrial Description of Change
*B *C *D *E
130114 210076 259010 308437
10/28/03 See ECN See ECN See ECN
RGL RGL RGL RGL
Document #: 38-07557 Rev. *E
Page 9 of 9

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